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ADVANCE INFORMATION
8X931AA/8x931HA UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLERS
s 8X931AA Hubless USB Peripheral Controller s On-chip USB Transceivers s On-chip Phase-locked loop s FIFO Data Buffers -- Two Pairs of 8-byte Transmit and Receive FIFOs -- One Pair of 16-byte Transmit and Receive FIFOs -- Supports Isochronous and Non-isochronous Data s Automatic FIFO Management s Three USB Interrupt Vectors -- Endpoint Transmit/Receive Done -- Start of Frame -- Global Suspend/Resume/USB Reset s Regulated 3V Output for Root Port Pullup Resistor s On-chip ROM Options -- 0 or 8 Kbytes s 256 bytes On-chip Data RAM s Four Input/Output Ports s MCS(R) 51 UART s Three 16-bit Timer/Counters s Keyboard Control Interface s Four Dedicated LED Driver Outputs s 6- or 12-MHz Crystal Operation -- Low Clock Mode (3MHz) s 8x931HA Includes all 8X931AA Features s 8x931HA USB Hub has One Internal Downstream, and Four External Downstream Ports -- Universal Serial Bus Specification 1.0 Compliant -- Serves as both USB Hub and USB Embedded Function (Internal Port) s USB Hub -- Connectivity Management -- Downstream Device Connect/Disconnect Detection -- Power Management, Including Suspend and Resume -- Bus Fault Detection and Recovery -- Full and Low Speed Downstream Device Support s Hub Endpoint Done Interrupt s Output Pin for Port Power Switching s Input Pin for Overcurrent Detection s Hub FIFO Data Buffers -- One Pair of 8-byte Transmit and Receive FIFOs -- One 1-byte Transmit Register s Embedded Function FIFO Data Buffers -- Same as the 8X931AA s 12-MHz Crystal Operation -- Low Clock Mode (3MHz)
The 8X931AA and 8x931HA USB peripheral controllers are based on the MCS(R)51 microcontroller. They consist of standard 8XC51Fx peripherals plus a USB module. The 8x931HA USB module provides both USB hub and USB embedded function capabilities. The 8x931HA supports USB hub functionality, embedded function, suspend/resume modes, isochronous/non-isochronous transfers, and is USB rev 1.0 specification compliant. The USB module contains one internal and 4 external downstream ports and integrates the USB transceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and transmit/receive FIFOs. The 8X931AA is a hubless USB peripheral controller which contains the same feature set as the 8x931HA hub controller except for the hub module. The 8X931AA/HA uses the standard instruction set of the MCS 51 architecture.
COPYRIGHT (c) INTEL CORPORATION, 1997
November 1997
Order Number: 273108-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation Literature Sales PO Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725
COPYRIGHT (c) INTEL CORPORATION, 1997
CONTENTS
1.0 About This Document.......................................................................................................... 1 1.1 Additional Information Sources ...................................................................................... 1 1.2 Electronic Information..................................................................................................... 1 1.3 Product Summary........................................................................................................... 2 2.0 Nomenclature Overview ...................................................................................................... 4 3.0 Pinout .................................................................................................................................. 6 3.0.1 8x931HA 68-pin PLCC Package ..................................................................................6 3.0.2 8X931AA 68-pin PLCC Package ..................................................................................7 4.0 Signals .............................................................................................................................. 10 5.0 Electrical Characteristics ................................................................................................... 13 5.1 Operating Frequencies ................................................................................................. 14 5.2 DC Characteristics........................................................................................................ 15 5.3 Explanation of Timing Symbols .................................................................................... 17 5.4 System Bus AC Characteristics.................................................................................... 18 5.4.1 System Bus Timing Diagrams ....................................................................................19 5.5 AC Characteristics -- Synchronous Mode 0 ................................................................ 21 5.6 External Clock Drive ..................................................................................................... 22 5.7 Testing Waveforms ...................................................................................................... 23 6.0 Thermal Characteristics .................................................................................................... 24 7.0 Design Considerations ...................................................................................................... 24 7.1 Low Clock Mode Frequency......................................................................................... 24 7.2 Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO ................................. 24 7.3 Series Resistor Requirement for Impedance Matching ................................................ 24 7.4 Pullup Resistor Requirement for 8X931AA/HA devices................................................ 24 7.5 Powerdown Mode Cannot Be Invoked Before USB Suspend ...................................... 24 7.6 Unused Downstream Ports........................................................................................... 24 7.7 ECAP Usage to Supply 3.0 to 3.6 Volts for 1.5K Ohm Pullup ...................................... 24 8.0 8X931AA/HA Errata ........................................................................................................... 25 9.0 Datasheet Revision History ............................................................................................... 25
iii
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Figures
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
8x931 Functional Block Diagram..........................................................................................2 8x931HA USB Module Block Diagram .................................................................................3 Product Nomenclature .........................................................................................................4 8x931HA 68-pin PLCC Package ..........................................................................................6 8X931AA 68-pin PLCC Package ..........................................................................................7 8X931AA/HA External Program Memory Read ..................................................................19 8X931AA/HA External Data Memory Read ........................................................................20 8X931AA/HA External Data Memory Write.........................................................................20 Serial Port Waveform -- Synchronous Mode 0..................................................................21 External Clock Drive Waveforms........................................................................................22 AC Testing Input, Output Waveforms.................................................................................23 Float Waveforms ................................................................................................................23
Tables
1. 2. 3. 5. 4. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.
Related Documentation........................................................................................................1 Electronic Information ..........................................................................................................1 Description of Product Nomenclature...................................................................................4 8X931AA Proliferation Options .............................................................................................5 8x931HA Proliferation Options .............................................................................................5 68-pin PLCC Pin Assignment...............................................................................................8 68-pin PLCC Signal Assignments Arranged by Functional Category ..................................9 Signal Description ..............................................................................................................10 8X931AA/8x931HA Supply Voltages..................................................................................13 8x931HA Operating Frequency..........................................................................................14 8X931AA Operating Frequencies .......................................................................................14 DC Characteristics at Operating Conditions.......................................................................15 AC Timing Symbol Definitions...........................................................................................17 External Bus Characteristics ..............................................................................................18 Serial Port Timing -- Synchronous Mode 0 .......................................................................21 External Clock Drive...........................................................................................................22 Thermal Characteristics .....................................................................................................24 Vcc and Typical ECAP Voltages ........................................................................................25
iv
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
1.0
ABOUT THIS DOCUMENT
1.2
Electronic Information
This data sheet contains advance information about Intel's 8X931AA and 8x931HA Universal Serial Bus peripheral controllers, based on the MCS(R)51 peripheral controller, which includes a functional overview, mechanical data, targeted electrical specifications (simulated), and bus functional waveforms. A detailed functional description, other than parametric performance, is published in the 8X931AA, 8x931HA Universal Serial Bus Peripheral Controller User's Manual (273102-001).
We offer a variety of technical and product information through the World Wide Web (see Table 2 for URL) and through FaxBack service which is an on-demand publishing system that sends documents to your fax machine. You can get product announcements, change notifications, product literature, device characteristics, design recommendations, and quality and reliability information 24 hours a day, 7 days a week. Just dial the telephone number and respond to the system prompts.
1.1
Additional Information Sources
Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. Intel Corporation Literature Sales PO Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 Table 1. Related Documentation Document Title Order/Contact Intel Order #273102-001 Intel Order #272904
8X931AA, 8x931HA Universal Serial Bus Peripheral Controller User's Manual Universal Serial Bus Specification, Rev. 1.0
Table 2. Electronic Information Document Title Intel's World-Wide Web (WWW) Location: Customer Support (US and Canada): FaxBack Service:
Order/Contact http://www.intel.com/design/usb/ 800-628-8686
US and Canada Europe worldwide
Application Bulletin Board Service:
800-628-2283 +44(0)793-496646 916-356-3105
up to 14.4-Kbaud line, worldwide dedicated 2400-baud line, worldwide Europe
916-356-3600 916-356-7209 +44(0)793-496340
ADVANCE INFORMATION
1
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
1.3
Product Summary
Data Address Register
RAM
ROM
Program Address Register
Program Counter
Upstream Port
USB Module B ACC
Stack Pointer
ALU
Data Pointer
Downstream Ports HA only
Instruction Sequencer
On-chip Peripherals
Clock and Reset
Parallel Ports
A4518-01
Figure 1. 8x931 Functional Block Diagram
2
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
USB External Downstream Ports Transceiver USB Upstream Port (Hub Root Port) DM0 DP0 Transceiver Repeater Transceiver Transceiver Transceiver DM2 DP2 DM3 DP3 DM4 DP4 DM5 DP5
Serial Bus Interface Engine (SIE)
Hub Interface Unit (HIU) Control
Function Interface Unit (FIU)
Transmit/Receive Bus To CPU
Data Bus
Control
FIFOs
A5247-01
Figure 2. 8x931HA USB Module Block Diagram
ADVANCE INFORMATION
3
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
2.0
NOMENCLATURE OVERVIEW
X
Te
XX
ck Pa
8
X
Pr og
X
Pr
XXXXX
XX
ed pe eS v ic De ily am tF uc od on Pr ati ns rm tio nfo Op sI ry mo Me oc
Table 3. Description of Product Nomenclature Parameter Temperature and Burn-in Packaging Options Program Memory Options Options no mark N 0 3 Process and Voltage Information Product Family no mark 931Hx Description Commercial operating temperature range (0oC to 70oC) with Intel standard burn-in Plastic Leaded Chip Carrier (PLCC) Without ROM With ROM CHMOS Advanced 8-bit microcontroller architecture with on-chip Universal Serial Bus Hub and Function capability. Indicates ROM size, RAM size, and quantity of external downstream ports (see Table 4). Advanced 8-bit microcontroller architecture with on-chip Universal Serial Bus Function capability. Indicates ROM size, RAM size, and quantity of external downstream ports (see Table 5). 6 or 12 MHz crystal (8X931AA), 12MHz crystal (8x931HA)
mp
es
ra
ing ag
931Ax
atu er
m
a re
Figure 3. Product Nomenclature
ns tio ns Op tio -in Op rn Bu
nd
A2815-01
Device Speed
no mark
4
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 4. 8x931HA Proliferation Options Part Name N80931HA N83931HA ROM Size 0 8 Kbytes RAM Size 256 bytes 256 bytes Package 68-pin PLCC 68-pin PLCC
Table 5. 8X931AA Proliferation Options Part Name N80931AA N83931AA ROM Size 0 8 Kbytes RAM Size 256 bytes 256 bytes Package 68-pin PLCC 68-pin PLCC
ADVANCE INFORMATION
5
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
3.0
3.0.1
PINOUT
8x931HA 68-pin PLCC Package
Figure 4 illustrates a diagram of the 8x931HA PLCC package. Table 6 and Table 7 contain indexes of the pin arrangement. Table 8 contains the signal descriptions for all pins. .
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A8 / P2.0 / KSO8 A9 / P2.1 / KSO9 A10 / P2.2 / KSO10 A11 / P2.3 / KSO11 A12 / P2.4 / KSO12 A13 / P2.5 / KSO13 A14 / P2.6 / KSO14 A15 / P2.7 / KSO15 VSS VCC EA# ALE PSEN# UPWEN# VSS Reserved (NC) Reserved (NC)
AD7 / P0.7 / KSI7 AD6 / P0.6 / KSI6 AD5 / P0.5 / KSI5 AD4 / P0.4 / KSI4 AD3 / P0.3 / KSI3 AD2 / P0.2 / KSI2 AD1 / P0.1 / KSI1 AD0 / P0.0 / KSI0 VSS VCC P3.0 / OVRI# P3.1 / SOF# P3.2 / INT0# P3.3 / INT1# P3.4 / T0 / KSO16 P3.5 / T1 / KSO17 P3.6 / WR# / KSO18
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8x931Hx
View of component as mounted on PC board
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
DP4 DM4 DP5 DM5 VCC DP0 DM0 ECAP VSS VCC VSS DP3 DM3 VSS DP2 DM2 LED0
Note: Reserved pins must be left unconnected.
A5340-02
Figure 4. 8x931HA 68-pin PLCC Package
6
P3.7 / RD# / KSO19 P1.0 / T2 / KSO0 P1.1 / T2EX / KSO1 P1.2 / KSO2 P1.3 / KSO3 P1.4 / KSO4 P1.5 / KSO5 P1.6 / RXD / KSO6 P1.7 / TXD / KSO7 LED3 LED2 XTAL1 XTAL2 AVCC RST PLLSEL LED1
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
3.0.2
8X931AA 68-pin PLCC Package
Figure 5 illustrates a diagram of the 8X931AA PLCC package. Table 6 and Table 7 contain indexes of the pin arrangement. Table 8 contains the signal descriptions for all pins.
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A8 / P2.0 / KSO8 A9 / P2.1 / KSO9 A10 / P2.2 / KSO10 A11 / P2.3 / KSO11 A12 / P2.4 / KSO12 A13 / P2.5 / KSO13 A14 / P2.6 / KSO14 A15 / P2.7 / KSO15 VSS VCC EA# ALE PSEN# FSSEL VSS Reserved (NC) Reserved (NC)
AD7 / P0.7 / KSI7 AD6 / P0.6 / KSI6 AD5 / P0.5 / KSI5 AD4 / P0.4 / KSI4 AD3 / P0.3 / KSI3 AD2 / P0.2 / KSI2 AD1 / P0.1 / KSI1 AD0 / P0.0 / KSI0 VSS VCC P3.0 P3.1 / SOF# P3.2 / INT0# P3.3 / INT1# P3.4 / T0 / KSO16 P3.5 / T1 / KSO17 P3.6 / WR# / KSO18
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8x931Ax
View of component as mounted on PC board
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Reserved (NC) Reserved (NC) Reserved (NC) Reserved (NC) VCC DP0 DM0 ECAP VSS VCC VSS Reserved (NC) Reserved (NC) VSS Reserved (NC) Reserved (NC) LED0
Note: Reserved pins must be left unconnected.
A5348-02
Figure 5. 8X931AA 68-pin PLCC Package
ADVANCE INFORMATION
P3.7 / RD# / KSO19 P1.0 / T2 / KSO0 P1.1 / T2EX / KSO1 P1.2 / KSO2 P1.3 / KSO3 P1.4 / KSO4 P1.5 / KSO5 P1.6 / RXD / KSO6 P1.7 / TXD / KSO7 LED3 LED2 XTAL1 XTAL2 AVCC RST PLLSEL LED1
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
7
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 6. 68-pin PLCC Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Name VSS A15/P2.7/KSO15 A14/P2.6/KSO14 A13/P2.5/KSO13 A12/P2.4/KSO12 A11/P2.3/KSO11 A10/P2.2/KSO10 A9/P2.1/KSO9 A8/P2.0/KSO8 AD7/P0.7/KSI7 AD6/P0.6/KSI6 AD5/P0.5/KSI5 AD4/P0.4/KSI4 AD3/P0.3/KSI3 AD2/P0.2/KSI2 AD1/P0.1/KSI1 AD0/P0.0/KSI0 VSS VCC P3.0/ OVRI# P3.1/SOF# P3.2/INT0# P3.3/INT1#
Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Name P3.4/T0/KSO16 P3.5/T1/KSO17 P3.6/WR#/KSO18 P3.7/RD#/KSO19 P1.0/T2/KSO0 P1.1/T2EX/KSO1 P1.2/KSO2 P1.3/KSO3 P1.4/KSO4 P1.5/KSO5 P1.6/KSO6/RXD P1.7/KSO7/TXD LED3 LED2 XTAL1 XTAL2 AVCC RST PLLSEL LED1 LED0 Reserved / DM2

Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VSS
Name Reserved/ DM3 Reserved/ DP3 VSS VCC VSS ECAP DM0 DP0 VCC Reserved/ DM5 Reserved/ DP5 Reserved/ DM4 Reserved/ DP4 Reserved (NC) Reserved (NC) VSS FSSEL/ UPWEN# PSEN# ALE EA# VCC
Reserved/ DP2
Specific to the 8X931AA Specific to the 8x931HA
8
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 7. 68-pin PLCC Signal Assignments Arranged by Functional Category Address & Data Name A15/P2.7/KSO15 A14/P2.6/KSO14 A13/P2.5/KSO13 A12/P2.4/KSO12 A11/P2.3/KSO11 A10/P2.2/KSO10 A9/P2.1/KSO9 A8/P2.0/KSO8 AD7/P0.7/KSI7 AD6/P0.6/KSI6 AD5/P0.5/KSI5 AD4/P0.4/KSI4 AD3/P0.3/KSI3 AD2/P0.2/KSI2 AD1/P0.1/KSI1 AD0/P0.0/KSI0 Pin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input/Output Name P1.0/T2/KSO0 P1.1/T2EX/KSO1 P1.2/KSO2 P1.3/KSO3 P1.4/KSO4 P1.5/KSO5 P1.6/KSO6 P1.7/KSO7 P3.0/ OVRI# P3.1/SOF# P3.2/INT0# P3.3/INT1# P3.4/T0/KSO16 P3.5/T1/KSO17 P3.6/WR#/KSO18 P3.7/RD#/KSO19
USB Pin 28 29 30 31 32 33 34 35 20 21 22 23 24 25 26 27 PLLSEL DM0 DP0 Reserved/ DM5 Reserved / DP5 Reserved/

Name
Pin 42 54 55 57 58 45 46 48 49 53 59 60
Reserved/ DM2 DP2
Reserved/ DM3 Reserved / DP3 ECAP Reserved/ DM4 Reserved/ DP4 FSSEL /UPWEN# OVRI#

64 20
Processor Control Name P3.2/INT0# P3.3/INT1# RST Pin 22 23 41 VSS XTAL1 XTAL2
Power & Ground Name VCC AVCC Pin 19,51, 56,68 40 1,18, 47,50, 52,63
Bus Control & Status Name P3.6/WR#/KSO18 P3.7/RD#/KSO19 PSEN# Pin 26 27 65
38 39
ALE EA#
66 67
Specific to the 8X931AA Specific to the 8x931HA
ADVANCE INFORMATION
9
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
4.0
SIGNALS
Table 8. Signal Description (Sheet 1 of 3)
Signal Name A15:8 AD7:0 ALE
Type O I/O O
Description Address Lines. Upper byte of external memory address. Address/Data Lines. Lower byte of external memory address multiplexed with data Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. Analog VCC. A separate VCC input for the phase-locked loop circuitry. USB Port 0. Root port. Upstream port to the host PC. DP0 and DM0 are the differential data plus and data minus signals of USB port 0. These lines do not have internal pullup resistors. Provide an external 1.5 K pullup resistor at DP0 so the device indicates to the host that it is a full-speed device; or provide an external 1.5 K pullup resistor at DM0 so the device indicates to the host that it is a low-speed device. NOTE: DP0 low AND DM0 low signals an SE0 (USB reset), causing the 8x931 to stay in reset. USB External Downstream Ports 2, 3, 4,5. These pins are the differential data plus and data minus lines for the four USB external downstream ports. These lines do not have internal pulldown resistors. Provide an external 15 K pulldown resistor at each of these pins. See "Design Considerations" on page 24. External Access. Directs program memory accesses to onchip or off-chip code memory. For EA# strapped to ground, all program memory accesses are off-chip. For EA# strapped to VCC, program accesses on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground. External Capacitor. Connect a 1 F or larger capacitor between this pin and V SS to ensure proper operation of the differential line drivers. May be used to supply 3.0v to 3.6v for 1.5K pullup resistor connected to USB Port 0. See "Design Considerations" on page 24. Full Speed Select. Applies to the 8X931AA only. If this pin is high, full speed USB data rate is selected (12Mbps). If pin is low, low speed USB data rate is selected (1.5 Mbps). Refer to Table 11.
Alternate Function P2.7:0/KS08:15 P0.7:0/KSI0:7 --
AVCC DM0, DP0
PWR I/O
-- --
DM2, DP2 DM3, DP3 DM4, DP4 DM5, DP5 EA#
I/O
--
I
--
ECAP
I
--
FSSEL
--
10
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 8. Signal Description (Sheet 2 of 3) Signal Name INT1:0# Type I Description External Interrupts 0 and 1. These inputs set the IE1:0 interrupt flags in the TCON register. Bits IT1:0 in TCON select the triggering method: edge-triggered (high-to-low) or level triggered (active low). INT1:0 also serves as external run control for timer1:0 when selected by GATE1:0# in TCON. Keyboard Scan Input. Schmitt-trigger inputs with firmwareenabled internal pullup resistors used for the input side of the keyboard scan matrix. Keyboard Scan Output. Quasi-bidirectional ports with weak internal pullup resistors used for the output side of the keyboard scan matrix. Alternate Function P3.3:2
KSI7:0
I
AD7:0/P0.7:0
KSO19 KSO18 KSO17:16 KSO15:8 KSO7:0 LED3:0
O
P3.7/RD# P3.6/WR# P3.5:4/T1:0 A15:8/P2.7:0 P1.7:0 --
O
LED Drivers. Designed to drive LEDs connected directly to VCC. The current each driver is capable of sinking is given as VOL2 in the datasheet. Overcurrent Sense. Sense input to indicate an overcurrent condition on an external down-stream port. Active low with an internal pullup. Port 0. Eight-bit, open-drain, bidirectional I/O port. Port 0 pins have Schmitt trigger inputs. Port 1. Eight-bit quasi-bidirectional I/O port with internal pullups. Port 2. Eight-bit quasi-bidirectional I/O port with internal pullups. Port 3. Eight-bit quasi-bidirectional I/O port with internal pullups.
OVRI#
I
P3.0
P0.7:0 P1.7:0 P2.7:0 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 PLLSEL
I/O I/O I/O I/O
AD7:0/KSI7:0 KSO7:0 A15:8/KSO15:8 OVRI# SOF# INT0# INT1# T0/KSO16 T1/KSO17 WR#/KSO18 RD#/KSO19 --
I
Phase-locked Loop Select. For normal operation using the 8x931HA, connect PLLSEL to logic high. PLLSEL = 0 is used for factory test only. (See Table 10). For 8X931AA operation, see Table 11. Program Store Enable. Read signal output. Asserted for read accesses to external program memory. Read. Read signal output. Asserted for read accesses to external data memory. Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.
PSEN# RD# RXD
O O I/O
-- P3.7/KSO19 P1.6
ADVANCE INFORMATION
11
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 8. Signal Description (Sheet 3 of 3) Signal Name RST Type I Description Reset. Reset input to the chip. Holding this pin high for two machine cycles while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and VCC. Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. SOF# O Start of Frame. Start of frame pulse. Active low. Asserted for 8 states when frame timer is locked to USB frame timing and SOF token or artificial SOF is detected. Timer 1:0 External Clock Input. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. USB Power Enable. A low signal on this pin applies power to the external downstream ports. Supply Voltage. Connect this pin to the +5v supply voltage. Use a 0.1f decoupling capacitor for each Vcc pin. Circuit Ground. Connect this pin to ground. Write. Write signal output to external memory. Oscillator Amplifier Input. When implementing the on-chip oscillator, connect the external crystal or ceramic resonator across XTAL1 and XTAL2. If an external clock source is used, connect it to this pin. Oscillator Amplifier Output. When implementing the on-chip oscillator, connect the external crystal or ceramic resonator across XTAL1 and XTAL2. If an external oscillator is used, leave XTAL2 unconnected. P3.1 -- Alternate Function
T1:0 T2
I I/O
P3.5:4/KSO17:16 P1.0
T2EX
I
P1.1
TXD
O
P1.7
UPWEN# VCC VSS WR# XTAL1
O PWR GND O I
-- -- -- P3.6/KSO19 --
XTAL2
O
--
12
ADVANCE INFORMATION
8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice.Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias................... -40C to +85C Storage Temperature .................................. -65C to +150C Voltage on Any Pins to VSS .............................-0.5 V to +6.5 V IOL per I/O Pin ................................................................. 15 mA Power Dissipation (1) ..................................................... 1.5 W
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias): Commercial ........................................................ -0C to +70C VCC (Digital Supply Voltage) .......................... 4.40 V to 5.25 V VSS ...................................................................................... 0 V AVCC (Analog Supply Voltage) ...................... 4.40 V to 5.25 V FOSC ............................................................................. 12 MHz
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTE: 1. Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.
Table 9. 8X931AA/8x931HA Supply Voltages Parameter Supply Voltage
Condition
Symbol 8x931HA Vcc/Vbus 8X931AA Vcc/Vbus
Min 4.40V 4.15V
Max 5.25V 5.25V
For bus-powered device, voltage droop during hot plug may cause the supply voltage to drop to 4V worst case. The functionality of the device is supported at this voltage.
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.1
Operating Frequencies
Table 10. 8x931HA Operating Frequency XTAL1 Frequency (FOSC) - 12 MHz Internal Frequency (FCLK) (2) - 6 MHz (3) XTAL1 Clocks per State (TOSC/state) (3) - 2
PLLSEL
USB Rate (1)
Comments
0 (4) 1
- 12 Mbps (Full Speed)
- PLL On
NOTES: 1. The sampling rate is 4 times the USB rate. 2. The internal frequency, FCLK = 1/TCLK, is the clock signal distributed to the CPU and the on-chip peripherals, 3. Following device reset, the CPU and on-chip peripherals operate in low-clock mode (FCLK = 3 MHz) until the LC bit in the PCON register is cleared. In low clock mode, there are four TOSC periods per state. Low-clock mode does not affect the USB rate. 4. PLLSEL = 0 is used during factory test only.
.
Table 11. 8X931AA Operating Frequencies PLLSEL Pin 0 0 1 1 1 1 FSSEL Pin 0 0 0 0 1 1 LC Bit (1) 0 1 0 1 0 1 XTAL1 Frequency (MHz) 6 6 12 12 12 12 USB Rate (FS/LS) (2) LS LS LS LS FS FS Core Frequency FCLK (Mhz) 3 3 6 3 6 3
Comment
PLL Off PLL Off PLL Off PLL Off PLL On PLL On
NOTES: 1. Reset and power up routines set the LC bit in PCON to put the 8X931AA in low-clock mode (core frequency = 3 MHz) for lower ICC prior to device enumeration. Following completion of device enumeration, firmware should clear the LC bit to exit the low-clock mode. The user may switch the core frequency back and forth at any time, as needed. 2. USB rates: Low speed = 1.5 Mbps; Full speed = 12 Mbps. The USB sample rate is 4X the USB rate.
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.2
DC Characteristics
Table 12. DC Characteristics at Operating Conditions
Symbol VIL VIL1 VIH VIH1 VOL
Parameter Input Low Voltage (except EA#) Input Low Voltage (EA#) Input High Voltage (except XTAL1, RST) Input High Voltage (XTAL1, RST) Output Low Voltage (port 1, 2, 3) (2) Output Low Voltage (port 0, ALE, PSEN#, SOF#) (2) Output Low Voltage (LED 0, 1, 2, 3) Output High Voltage (port 1, 2, 3, ALE, PSEN#, SOF#) (3) Output High Voltage (port 0 in external address space) (3) Logical 0 Input Current (port 1,2,3) Input Leakage Current (port 0)
Min -0.5 0 0.2 VCC + 0.9 0.7 VCC
Typical (1)
Max 0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 2.0 3.0
Units V V V V V
Test Conditions
IOL = 100 A IOL = 1.6 mA IOL = 3.5 mA IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA
VOL1
V
VOL2 VOH
V V
IOL = 6 mA IOL = 22 mA IOH = -10 A IOH = -30 A IOH = -60 A
VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5 -50
VOH1
V
IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA
IIL
A
VIN = 0.45 V
ILI
10
A
VIN = VIL or VIH
NOTE: 1. Typical values are obtained using VCC = 5.0V, TA = 25C and are not guaranteed. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC specification when the address lines are stabilizing.
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 12. DC Characteristics at Operating Conditions (Continued) Symbol ITL Parameter Logical 1-to-0 Transition Current (Port 1, 2,3) RST Pulldown Resistor Pin Capacitance Powerdown Current USB suspend IDL ICC Idle Mode ICC Active ICC 145 175 40 30 70 50 UZDRV USB Drivers Output 10 25 K mA FCLK = 6 MHz FCLK = 3MHz mA FCLK =6 MHz FCLK =3 MHz 40 10 Min Typical (1) Max -650 Units A Test Conditions VIN = 2.0 V
RRST CIO IPD
100
K pF A FOSC = 12 MHz TA = 25C
NOTE: 1. Typical values are obtained using VCC = 5.0V, TA = 25C and are not guaranteed. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC specification when the address lines are stabilizing.
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.3
Explanation of Timing Symbols
Table 13 defines the timing symbols used in Tables 14 through 16 and the associated timing diagrams. They have the form TXXYY, where the character pairs represent a signal and its condition. Timing symbols represent the time between two signal / condition points. Table 13. AC Timing Symbol Definitions Symbol A C D L P Q R W Character H L V X Z High Low Valid, Setup No Longer Valid, Hold Floating (low impedance) Address: A15:8, A7:0 External Clock (XTAL1) Data In: D7:0 ALE: Address Latch Enable Program Store Enable (PSEN#) Data Out: D7:0 Read: RD# Write: WR# Condition Definition
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.4
System Bus AC Characteristics
Test Conditions: FOSC = 12 MHz. Rise and fall times = 10 ns. Capacitive loading on ALE, PSEN#, and port P0 = 100 pF. Capacitive loading on all other outputs = 80 pF. Table 14. External Bus Characteristics Symbol Parameter FOSC = 12 MHz, FCLK = 6 MHz Min FOSC TCLK TLHLL TAVLL TLLAX TPLAZ TLLIV TLLPL TPLPH TPLIV TPHIX TPHIZ TAVIV TLLRL, TLLWL TRLRH, TWLWH TLLDV TRLDV TRLAZ TRHDX TRHDz TAVRL, TAVWL XTAL1 Frequency 1/FCLK = 1/CPU Frequency ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low PSEN# Low to Address Float ALE Low to Instruction In Valid ALE Low to PSEN# Low PSEN# Pulse Width PSEN# Low to Instruction In Valid Instruction Hold after PSEN# High Instruction Float after PSEN# High Address Valid to Instruction Valid ALE Low to RD# or WR# Low RD# and WR# Pulse Width ALE Low to Data In Valid RD# Low to Data In Valid RD# Low to Address Float Data Hold After RD# High Data Float After RD# High Address Valid to RD# or WR# Low 244 0 23 2TCLK - 90 200 400 578 322 0 0 0.5TCLK - 60 0 63 312 300 1.5TCLK - 50 3TCLK - 100 4TCLK - 90 2.5TCLK - 95 0 53 205 77 0 0.5TCLK - 20 2.5TCLK - 105 1.5TCLK + 50 Max 12 0.25% 166.67 (Typical) 127 43 53 10 259 0.5TCLK - 30 1.5TCLK - 45 TCLK - 90 TCLK - 40 0.5TCLK - 40 0.5TCLK - 30 10 2TCLK - 75 Variable FCLK Min Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
Table 14. External Bus Characteristics (Continued) Symbol Parameter FOSC = 12 MHz, FCLK = 6 MHz Min TAVDV TRHLH, TWHLH TQVWX TQVWH TWHQX Address Valid to Data In Valid RD# or WR# High to ALE High Data Valid to WR# Transition Data Valid to WR# High Data Hold After WR# High 43 48 514 43 Max 661 123 0.5TCLK - 40 0.5TCLK - 35 3.5TCLK - 70 0.5TCLK - 40 Variable FCLK Min Max 4.5TCLK - 90 0.5TCLK + 40 ns ns ns ns ns Units
5.4.1
System Bus Timing Diagrams
TLHLL ALE TLLIV TAVLL PSEN# TLLAX Port 0 A7:0 TAVIV Port 2 A15:8 A15:8
A5280-02
TLLPL
TPLPH TPLIV TPLAZ TPHIX INSTR IN TPHIZ A7:0
Figure 6. 8X931AA/HA External Program Memory Read
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
ALE TLHLL PSEN# TLLDV TLLRL RD# TAVLL TLLAX Port 0 A7:0 from RI or DPL TAVRL Port 2 TAVDV P2.7:0 or A15:8 from DPH A15:8 from PCH
A5275-02
TRHLH
TRLRH TRLDV TRLAZ Data In
TRHDZ TRHDX A7:0 from PCL Inst. In
Figure 7. 8X931AA/HA External Data Memory Read
ALE TLHLL PSEN# TLLWL WR# TAVLL TLLAX Port 0 A7:0 from RI or DPL TAVWL Port 2 P2.7:0 or A15:8 from DPH A15:8 from PCH
A5276-01
TWHLH
TWLWH
TQVWX
TQVWH Data Out
TWHQX A7:0 from PCL Inst. In
Figure 8. 8X931AA/HA External Data Memory Write
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.5
AC Characteristics -- Synchronous Mode 0
TXLXL
TXD
TXHQX TQVXH
Set TI
2 3 4 5 6 7
RXD (Out)
0
1
TXHDV
TXHDX Valid Valid Valid Valid Valid Valid
Set RI
Valid
RXD (In)
Valid
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 9. Serial Port Waveform -- Synchronous Mode 0 Table 15. Serial Port Timing -- Synchronous Mode 0 Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid Min 12 TOSC 10 TOSC - 133 2 TOSC - 50 0 10 TOSC - 133 Max Units ns ns ns ns ns
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.6
External Clock Drive
TCLCH
VCC - 0.5 0.7 VCC
TCHCX
TCLCX 0.45 V
0.2 VCC - 0.1
TCHCL
TCLCL
A4119-01
Figure 10. External Clock Drive Waveforms
Table 16. External Clock Drive Symbol 1/TOSC TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency (FOSC) High Time Low Time Rise Time Fall Time Min 6 20 20 20 20 Max 12 Units MHz ns ns ns ns
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.7
Testing Waveforms
Inputs VCC - 0.5
0.45 V
Outputs 0.2 VCC + 0.9 0.2 VCC - 0.1 VIH MIN VOL MAX
AC inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 11. AC Testing Input, Output Waveforms
VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.
A4117-01
Figure 12. Float Waveforms
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
6.0
THERMAL CHARACTERISTICS
The microcontroller operates over the commercial temperature range from 0oC to 70oC. All thermal impedance data (see Table 17) is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 17. Thermal Characteristics Package Type 68-pin PLCC
condition can be seen on the oscilloscopes as excessive overshoot and undershoot. This condition can potentially introduce bit errors.
7.4
Pullup Resistor Requirement for 8X931AA/HA devices
JA N/A
JC N/A
The USB specification requires a pullup resistor to allow the host to identify which devices are low speed and which are full speed in order to communicate at the appropriate data rate. For 8x931HA hub devices (12 Mbps), use a 1.5K pullup resistor (to 3.0 V - 3.6 V; may use the ECAP pin.) on the DP0 line. 8X931AA devices can be either full speed or low speed; add a 1.5K pullup to the appropriate USB line.
Data unavailable at time of publication.
7.0 7.1
DESIGN CONSIDERATIONS Low Clock Mode Frequency
7.5
Powerdown Mode Cannot Be Invoked Before USB Suspend
During low clock mode, the internal clock FCLK distributed to the CPU and peripherals is 3 MHz. Peripheral timing and external bus accesses (including instruction fetch and data read/write) are affected. Refer to Table 10 and Table 11 for clock rates.
If the 8X931AA/HA is put into powerdown mode before receiving a USB suspend signal from the host, then a USB resume will not properly wake up the 8X931AA/HA from powerdown mode.
7.6
Unused Downstream Ports
7.2
Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO
If the receive FIFO is set as a dual packet mode, then it can receive two packets. Setting RXFFRC (in RXCON registers) to indicate FIFO Read Complete will not flush the entire FIFO; it will flush only the oldest packet. The read marker will be advanced to the location of the read pointer.
If the USB downstream ports are not used, it is still required that the two data lines be pulled low externally (similar to a disconnect) so that the inputs are not floating. This will eliminate the possibility of induced system noise. All USB data lines require 15K external pulldown resistors. Do not leave unused port(s) disconnected.
7.7
ECAP Usage to Supply 3.0 to 3.6 Volts for 1.5K Ohm Pullup
7.3
Series Resistor Requirement for Impedance Matching
Per USB rev. 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver must be between 29 and 44. To match the cable impedance, a series resistor of 27 to 33 should be connected to each USB line; i.e., on DP0 and on DM0. If the USB line is improperly terminated or not matched, then signal fidelity will suffer. This
For a self-powered or bus-powered device, when the voltage at the VCC pins are at 5.25v, the voltage at ECAP pin will be at approximately 3.6v. If the VCC pin is at 4.65v [Min, Vbus Powered (host or hub) Port specification], the voltage at the ECAP pin will be at approximately 3.2v (refer to Table 18 below). The capability for this pin to supply the 3.0v to 3.6v voltage to the 1.5K USB pullup terminator depends upon the VCC voltage level.
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8X931AA, 8x931HA USB PERIPHERAL CONTROLLER
For a bus-powered device that is connected to a bus-powered hub, when the voltage at the Vcc pins (in the bus-powered devices) are at 4.28v, the voltage at ECAP pin will be at approximately 3.0v. If the Vcc voltage drops below 4.28v, the ECAP pin can not supply voltage above 3.0 v for the 1.5K USB pullup terminator. NOTE: The typical ECAP values, listed in the table below, reflect a 1 F capacitor connection between the ECAP pin and ground. Table 18. Vcc and Typical ECAP Voltages VCC ECAP Pin 5.25v 5.00v 4.65v 4.40v 4.28v 3.6v 3.5v 3.2v 3.1v 3.0v
8.0
8X931AA/HA ERRATA
The 8X931AA/HA may contain design defects or errors known as errata. Characterized errata that may cause the 8X931AA/HA's operational behavior to deviate from published specifications are documented in a specification update. Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
9.0
DATASHEET REVISION HISTORY
Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This is the original version of the datasheet.
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